register-transfer-level

What logic will be created if variables in the sensitivity list are missing

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问题 This was an interview question asked by a top 10 company of US. Code 1: always @(a or b or sel) begin if (sel == 1) c = a; else if (sel == 0) c =b; end This will create a mux. Code 2: Now "SEL" is removed from sensitivity. Will it still create mux? For the code below? If not, what logic will be created? always @(a or b) begin if (sel == 1) c = a; else if (sel == 0) c =b; end 回答1: Yes, this will still synthesize to a multiplexer 1 . A synthesis tool will interpret this RTL as if the

What logic will be created if variables in the sensitivity list are missing

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Override size of a parameter that is an array of a struct in systemverilog

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问题 i have a module parameter that is an array of a predefined struct. I set the default size of this array as 1 element. The idea is to override it with the appropriate size at the time of instantiation. The way i show below doesn't override the size. It only overides the first value. I can see why it would do this as the size field is not parameterized. Is there a better way than to pass a parameter for the size? Thank you for the help. module reg_slave #(parameter reg_pkg::defval_pair [0:0]

System Verilog always_latch vs. always_ff

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问题 Just started learning System Verilog. I am confused about the usage of statements always_ff and always_latch . The former would be used as: always_ff @ (posedge clk) begin a <= b; end while the latter: always_latch begin a <= b; end The first is activated just by the positive edge of the clock and coupled with non-blocking assignment produces a FF. The always_latch is obviously thought to represent a latch, but then why use a non-blocking assignment? Wouldn't be better using a always_comb

How to use clock gating in RTL?

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问题 I am clock gating some latch and logic in my design. I don't have much experience in synthesis and place & route. What is the proper way to implement clock gating in RTL? Example1: always_comb begin gated_clk = clk & latch_update_en; end always_latch begin if(gated_clk) begin latch_data <= new_data; end end Example2: I stumbled into a RTL examples while doing some research about good practices in RTL clock gating. That example implemented the above code like this: clock_gator cg_cell (.clk

Verilog : Memory block Instantiation

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问题 I used the following code to instantiate 2-D memory in a verilog reg [15:0] data_pattern_even [3:0] = {16'hFFFF,16'hFFFF,16'hFFFF,16'hFFFF}; reg [15:0] data_pattern_ev [3:0] = {16'hFFFF,16'hFFFF,16'hFFFF,16'hFFFF}; This instantiation worked all right in Simulation but failed to work when actually synthesised and RTL analysis done Can anyone elaborate to me as in how that is possible? 回答1: For Altera devices: https://www.altera.com/support/support-resources/design-examples/design-software

Defining parameters from command line in (system)verilog simulation

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问题 I have a module ''constrained'' with several delays as parameters. I want to simulate all the possible configuration of the delays in the module. As I have a lot of configuration to test, I do not want to instantiate all the configuration possible in the same testbench. The idea I had was to launch one simulation for each configuration. I thought about generating a simulation script that will launch the simulation for each delay configuration. The problem is that I cannot manage to override

Defining parameters from command line in (system)verilog simulation

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I have a module ''constrained'' with several delays as parameters. I want to simulate all the possible configuration of the delays in the module. As I have a lot of configuration to test, I do not want to instantiate all the configuration possible in the same testbench. The idea I had was to launch one simulation for each configuration. I thought about generating a simulation script that will launch the simulation for each delay configuration. The problem is that I cannot manage to override the parameters of the module with the values retrieved from the command-line. I used $value$plusargs(

How to define and initialize a vector containing only ones in Verilog?

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问题 If I want to declare a 128 bit vector of all ones, which one of these methods is always correct? wire [127:0] mywire; assign mywire = 128'b1; assign mywire = {128{1'b1}}; assign mywire = 128'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF; 回答1: As a quick simulation would prove, assign mywire = 128'b1; does not assign all bits of mywire to 1. Only bit 0 is assigned 1. Both of the following always assign all 128 bits to 1: assign mywire = {128{1'b1}}; assign mywire = 128'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF;

How to use clock gating in RTL?

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I am clock gating some latch and logic in my design. I don't have much experience in synthesis and place & route. What is the proper way to implement clock gating in RTL? Example1: always_comb begin gated_clk = clk & latch_update_en; end always_latch begin if(gated_clk) begin latch_data <= new_data; end end Example2: I stumbled into a RTL examples while doing some research about good practices in RTL clock gating. That example implemented the above code like this: clock_gator cg_cell (.clk(clk), .en(latch_update_en), .scan_en(scan_en_in), .gated_clk(gated_clk)); always_latch begin if(gated_clk