processor

问题 We know that the direct-mapped caches are better than set-associative cache in terms of the cache hit time as there is no search involved for a particular tag. On the other hand, set-associative caches usually show better-hit rate than direct-mapped caches. I read that the modern processors try to combine the benefit of both by using a technique called way-prediction. Where they predict the line of the given set where the hit is most likely to happen and search only in that line. If the

问题 I'm using Windows Server 2016 with 72 cores. I see that there are 2 groups of processors. my .net app will use one or the other groups. I need to be able to force my app to use the Group of my choice. I see a code example below but I am unable to make it work. I might be passing the wrong variables. I want the app to pick group 1 and all the processors then group 2 and all the processors. my question is how do i force my .net app to use group 1 or group 2? i am not sure if the link below will

问题 I was wondering, how does processors know when to stop executing a program. Or rather, when to stop the "fetch, decode execute" cycle. I have thought of different ways but not sure which is the correct one or if they are all wrong. 1- Maybe there is a special instruction at the end automatically added by the assembler to let the processor know this is the end. 2- When it reach an invalid memory (But how does it recognize that). 3- It loops and re-run the program, but again how does it

问题 We know that two instructions can be reordered by an OoOE processor. For example, there are two global variables shared among different threads. int data; bool ready; A writer thread produce data and turn on a flag ready to allow readers to consume that data. data = 6; ready = true; Now, on an OoOE processor, these two instructions can be reordered (instruction fetch, execution). But what about the final commit/write-back of the results? i.e., will the store be in-order? From what I learned,

问题 Let's focus on uniprocessor computer systems. When a process gets created, as far as I know, the page table gets set up which maps the virtual addresses to the physical memory address space. Each process gets its own page table, stored in the kernel address space. But how does the MMU choose the right page table for the process since there is not only one process running and there will be many context switches happening? Any help is appreciated! Best, Simon 回答1: Processors have a privileged

问题 I have recently been interested in understanding low level computing. I understand that today's widely used computers follow x86/x86-64 architecture. To my understanding, architecture, more specifically Instruction Set Architecture (ISA) is the set of instructions that the programmer is able to issue to the CPU. The first question, Is the ISA keeps evolving or remains the same? I think that it keeps evolving (meaning new instructions keeps getting added/previous instructions modified?) but

问题 I have recently been interested in understanding low level computing. I understand that today's widely used computers follow x86/x86-64 architecture. To my understanding, architecture, more specifically Instruction Set Architecture (ISA) is the set of instructions that the programmer is able to issue to the CPU. The first question, Is the ISA keeps evolving or remains the same? I think that it keeps evolving (meaning new instructions keeps getting added/previous instructions modified?) but

问题 I want to understand the importance of Q flag in ARM Processor. I know there are certain instructions like QADD,QSUB etc. But I need to understand this with some examples which will clarify the concept. Please explain me. Thank you 回答1: This is explained in the "ARM Architecture Reference Manual" (ARM DDI 0100E): Bit[27] of the CPSR is a sticky overflow flag, also known as the Q flag. This flag is set to 1 if any of the following occurs: Saturation of the addition result in a QADD or QDADD

问题 I want to understand the importance of Q flag in ARM Processor. I know there are certain instructions like QADD,QSUB etc. But I need to understand this with some examples which will clarify the concept. Please explain me. Thank you 回答1: This is explained in the "ARM Architecture Reference Manual" (ARM DDI 0100E): Bit[27] of the CPSR is a sticky overflow flag, also known as the Q flag. This flag is set to 1 if any of the following occurs: Saturation of the addition result in a QADD or QDADD

问题 I am setting up my InstallShield to install my package as 64 bit (into Program Files not Program Files x86) by. My processor is: Intel(R) Core(TM) i7-2600 CPU InstallShield => General Information => Summary Information Stream => Template Summary From Intel32;1033 to Intel64;1033 And it gives me the general error message: This installation package is not supported by this processor Then I set the value to: Amd64;1033 or x64;1033 And it magically work. But weird thing is, my processor is Intel,