Verilog, FPGA, use of an unitialized register

Question

I have a question about what seems to me odd behavior of an AGC/SPI controller I\'m working on. It\'s done in Verilog, targeting a Xilinx Spartan 3e FPGA. The controller i

Answer 1

I answer in the context of FPGAs (I have most experience with Xilinx FPGAs); I disagree with Tim's answer.

When an FPGA is programmed and initialized, many internal resources are initialized to a known state. This includes all flip flops and block rams. By adding blanket reset logic throughout your design, you may make it significantly more complicated than it needs to be, if you could otherwise count on internal elements initializing to a known state. High fanout reset nets can make implementation of your design much more difficult for the router, and mapping your design into slices is also complicated by your choice of resets - especially asynchronous ones.

My suggestions:

• Use initialization values for your registers. Double check Xilinx XST documentation for the version you are using for supported syntax. Contrary to widely held belief, initialization values will be honored in most cases. The side benefit of doing this, is that the initial state of your chip will match the initial state of your simulation.
• Only reset necessary control signals and leave your datapath registers alone to allow more efficient mapping (for example, a pipeline into a shift register).

Answer 2

So my question is, is an uninitialized register supposed to assume a value of 0?

No, they assume x. For Synthesis you must reset as they may be holding any value. I have no FPGA experience but Nathan Farrington suggests that they are also reset/initialised.

For FPGA doing the following should be enough:

reg [4:0] state_reg = 'b0,

For Synthesis I would recommend doing this inside a reset clause.

always @(posedge clk or negedge reset) begin
  if (!reset) begin
    state_reg <= 'b0 ;
  end
  else begin
    ..
  end
end