Get internal signals of vhdl design in ncvhdl (alternative to modelsim's signal spy)

Question

In ModelSim you can use something like

in modelsim we can use init_signal_spy(\"../.../sig\", mysignal);

to get deep hierarchy signals. Is there a way to get

Answer 1

If Cadence tools support VHDL-2008, you can access signals, shared variables, or constants in other levels of your design via external names.

Direct usage is as follows.

A <= <<signal .tb_top.u_comp1.my_sig : std_logic_vector >>; 

Note that the object must be elaborated before the reference. Since VHDL designs are elaborated in order of instantiation later designs may reference into earlier ones.

Use an alias to create a local short hand name:

alias u1_my_sig is <<signal u1.my_sig : std_logic_vector >>; 

Path starts with:

• “.” = path starts at top level: “.tb_top.my_sig”
• “u1” = path starts from current level: “u1.my_sig”
• “^” = path starts from level above current: “^u2.my_sig”

Answer 2

As one can see here, the function is called nc_mirror.

 nc_mirror (destination => "destination",

           source => "source",

           verbose => "verbose"); 

It takes a destination and a source and does just the same as init_signal_spy does for modelsim. The third parameter is optional. Additionally it supports mirroring arrays or records.

In this interesting answer a wrapper package is provided that converts the nc_mirror or init_spy_signal (and others) to a function "probe".