How to pass array structure between two verilog modules

Question

I am trying to pass a array structure as reg [0:31]instructionmem[0:31] between two modules.

I coded it as follows :

Module No 1:

       mo         


        

Answer 1

This is not possible in Verilog. (See sec. 12.3.3, Syntax 12-4 of the Verilog 2005 standard document, IEEE Std. 1364-2005.)

Instead you should "flatten" the array and pass it as a simple vector, e.g.:

module module1(instructionmem);
  output [32*32-1:0] instructionmem;
  reg [31:0] instructionmem_array [31:0];

  genvar i;
  generate for (i = 0; i < 32; i = i+1) begin:instmem
    assign instructionmem[32*i +: 32] = instructionmem_array[i]; 
  end endgenerate
endmodule

module module2(instructionmem);
  input [32*32-1:0] instructionmem;
  reg [31:0] instructionmem_array [31:0];

  integer i;
  always @*
    for (i = 0; i < 32; i = i+1)
      instructionmem_array[i] = instructionmem[32*i +: 32];
endmodule

module test_bench(instructionmem);
  output [32*32-1:0] instructionmem;
  module1 m1(instructionmem);
  module2 m2(instructionmem);
endmodule