Multiple colons and equal sign in makefile (need explanation)

Question

This is only a segment of a makefile. I don\'t quite understand what is going on.

OBJS = $(SRCS:$(SRC)/%.cpp=$(OBJ)/%.o)
$(OBJS):$(OBJ)/%.o: $(SRC)/%.cpp |          


        

Answer 1

Suppose you've defined these three variables (and if you haven't, the rule won't work very well):

SRC = source_dir
OBJ = object_dir
SRCS = source_dir/foo.cpp source_dir/bar.cpp

Now consider the assignment

OBJS = $(SRCS:$(SRC)/%.cpp=$(OBJ)/%.o)

This is a substitution reference; it says "for anything in $(SRCS) that has the form $(SRC)/%.cpp, change it to $(OBJ)/%.o". So OBJS will evaluate to object_dir/foo.o object_dir/bar.o.

Now the rule:

$(OBJS):$(OBJ)/%.o: $(SRC)/%.cpp | print-opts
    $(cc-command)

Thuis is a static pattern rule. It specifies a list of targets ($(OBJS)), a target pattern ($(OBJ)/%.o) and a prerequisite pattern ($(SRC)/%.cpp). Make matches a target to the target pattern, and uses that to construct the prerequisite name. So if Make used this rule to build object_dir/foo.o, the stem would be foo and the prerequisite would be source_dir/foo.cpp.

(You didn't ask about | print-opts, so I assume that it's already clear.)