VHDL syntax error

Question

In my code, I have the following lines:

architecture Behavioral of L6 is

begin
with SEL select 
    Z <= \'1111110\' when \'0000\',
          \'00110000\         


        

Answer 1

VHDL uses the single quote for single bit literals, like '1' and 'Z'.

For bit vector literals, use double quotes "0000", etc.