Make and GCC are a great combo for really good dependency checking.
GCC can generate 'make' dependency files automatically (-MD commandline switch), so as to be able to rebuild all sourcefiles that depend upon a given header, for example.
I have some simple rules that I cut-n-paste into my makefiles:
# compile c files
%.o: %.c
${CC} ${CFLAGS} -c $< -MD -MF $(<:%.c=%.dep) -o $@
# compile c++ files
%.opp: %.cpp
${CPP} ${CPPFLAGS} -c $< -MD -MF $(<:%.cpp=%.dep) -o $@
Now if your object files are declared in say an OBJ_C and an OBJ_CPP list:
.PHONY: cleandep
cleandep:
rm -f $(OBJ_C:%.o=%.dep) $(OBJ_CPP:%.opp=%.dep)
-include $(OBJ_C:%.o=%.dep) $(OBJ_CPP:%.opp=%.dep)
Make can of course track dependencies with other projects and such, e.g. rebuilding a shared libary as necessary, too.
For example, if your other teams always put their latest DLLs on some shared folder:
myapp: ${SRC_CPP} ${LIB_DIR}other_team.lib
...
${LIB_DIR}other_team.lib: /shared_folder/latest/other_team.lib
cp /shared_folder/latest/other_team.lib ${LIB_DIR}other_team.lib