How to print out a variable in makefile

后端 未结 15 1056
臣服心动
臣服心动 2020-12-07 06:51

In my makefile, I have a variable \'NDK_PROJECT_PATH\', my question is how can I print it out when it compiles?

I read Make file echo displaying "$PATH" st

相关标签:
15条回答
  • 2020-12-07 07:13

    If you don't want to modify the Makefile itself, you can use --eval to add a new target, and then execute the new target, e.g.

    make --eval='print-tests: @echo TESTS $(TESTS) ' print-tests

    You can insert the required TAB character in the command line using CTRL-V, TAB

    example Makefile from above:

    all: do-something
    
    TESTS=
    TESTS+='a'
    TESTS+='b'
    TESTS+='c'
    
    do-something:
            @echo "doing something"
            @echo "running tests $(TESTS)"
            @exit 1
    
    0 讨论(0)
  • 2020-12-07 07:16

    if you use android make (mka) @echo $(NDK_PROJECT_PATH) will not work and gives you error *** missing separator. Stop." use this answer if you are trying to print variables in android make

    NDK_PROJECT_PATH := some_value
    $(warning $(NDK_PROJECT_PATH))
    

    that worked for me

    0 讨论(0)
  • 2020-12-07 07:17

    You can print out variables as the makefile is read (assuming GNU make as you have tagged this question appropriately) using this method (with a variable named "var"):

    $(info $$var is [${var}])
    

    You can add this construct to any recipe to see what make will pass to the shell:

    .PHONY: all
    all: ; $(info $$var is [${var}])echo Hello world
    

    Now, what happens here is that make stores the entire recipe ($(info $$var is [${var}])echo Hello world) as a single recursively expanded variable. When make decides to run the recipe (for instance when you tell it to build all), it expands the variable, and then passes each resulting line separately to the shell.

    So, in painful detail:

    • It expands $(info $$var is [${var}])echo Hello world
    • To do this it first expands $(info $$var is [${var}])
      • $$ becomes literal $
      • ${var} becomes :-) (say)
      • The side effect is that $var is [:-)] appears on standard out
      • The expansion of the $(info...) though is empty
    • Make is left with echo Hello world
      • Make prints echo Hello world on stdout first to let you know what it's going to ask the shell to do
    • The shell prints Hello world on stdout.
    0 讨论(0)
  • 2020-12-07 07:17

    You could create a vars rule in your make file, like this:

    dispvar = echo $(1)=$($(1)) ; echo
    
    .PHONY: vars
    vars:
        @$(call dispvar,SOMEVAR1)
        @$(call dispvar,SOMEVAR2)
    

    There are some more robust ways to dump all variables here: gnu make: list the values of all variables (or "macros") in a particular run.

    0 讨论(0)
  • 2020-12-07 07:20

    As per the GNU Make manual and also pointed by 'bobbogo' in the below answer, you can use info / warning / error to display text.

    $(error   text…)
    $(warning text…)
    $(info    text…)
    

    To print variables,

    $(error   VAR is $(VAR))
    $(warning VAR is $(VAR))
    $(info    VAR is $(VAR))
    

    'error' would stop the make execution, after showing the error string

    0 讨论(0)
  • 2020-12-07 07:22

    The problem is that echo works only under an execution block. i.e. anything after "xx:"

    So anything above the first execution block is just initialization so no execution command can used.

    So create a execution blocl

    0 讨论(0)
提交回复
热议问题