Can anyone help me to create a Verilog testbench?

Question

Can anyone help me create a testbench or just the input code for my following code? I\'m using XILINX.

module fsmb (input rst,clk,a,
             output reg          


        

Answer 1

Xilinx ISE will generate a skeleton test fixture automatically. Go to menu item Project->New Source. The dialog box will ask you to "Select Source Type" click "Verilog Test Fixture" and give it a name like testbench1 and click Next. Then it will then ask you which module in your project to associate with it. Select fsmb. Click Next and Finish.

You still have to tweak the testbench like setting the initial input values, generating a clock, and lifting reset after a few clocks.

Answer 2

Testbench 101

1. Create a new module (tb).
2. Create a reg for each input of your DUT.
3. Create a wire for each output of your DUT.
4. Create an instance of your DUT.
5. Connect your regs and wires to your DUT.
6. Generate a clock
7. Drive your other inputs
8. Create checkers for your outputs (I'll leave this up to you).

Example:

module tb;

reg rst,clk,a;
wire x;

initial begin
    clk = 0;
    forever #5 clk = ~clk;
end

initial begin
    rst = 1;
    a = 0;
    #50 rst = 0;
    #50 $finish;
end

fsmb fsmb (
    .clk    (clk),
    .rst    (rst),
    .a      (a),
    .x      (x)
);

endmodule

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Other simple testbench examples are provided on EDA playgound. You can sign up for a free account and look at samples such as: Published Playgounds -> D flip flop