Is there a simple example of how to generate verilog from Chisel3 module?

Question

I\'m looking for a simple howto to convert a simple Chisel3 module in Verilog.

I take Gcd source code given on official web page of chisel.

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Answer 1

Thank you for your interest in Chisel! We generally encourage people to use our chisel-template repo as a starting point for Chisel3 projects: https://github.com/ucb-bar/chisel-template

If you want to do the most barebones possible thing. Create this build.sbt and put it in the root directory for your project.

scalaVersion := "2.12.10"

resolvers ++= Seq(
  Resolver.sonatypeRepo("snapshots"),
  Resolver.sonatypeRepo("releases")
)

libraryDependencies += "edu.berkeley.cs" %% "chisel3" % "3.3.+"

Put the above GCD source code in GCD.scala and add the following to the file:

import chisel3.stage.{ChiselGeneratorAnnotation, ChiselStage}

object GCDDriver extends App {
  (new ChiselStage).execute(args, Seq(ChiselGeneratorAnnotation(() => new GCD)))
}

You can then generate the Verilog by running: sbt "runMain GCDDriver". The default output directory is the current directory.

You can see what command-line options are available by running sbt "runMain GCDDriver --help" For example --target-dir will let you change the target directory