Define compilation variables based on target for

Question

my c++ source file look for a specific variable passed from the makefile. when making a different target, this variable definition is different.

How can I define a

Answer 1

Do you mean something like this:

$ cat Makefile
BUILD := debug

cxxflags.debug := -g -march=native
cxxflags.release := -g -O3 -march=native -DNDEBUG
CXXFLAGS := ${cxxflags.${BUILD}}

all :
    @echo BUILD=${BUILD}
    @echo CXXFLAGS=${CXXFLAGS}

.PHONY : all

Output:

$ make
BUILD=debug
CXXFLAGS=-g -march=native

$ make BUILD=release
BUILD=release
CXXFLAGS=-g -O3 -march=native -DNDEBUG

Answer 2

What about that?

ifeq ($(MAKECMDGOALS),release)
    CFLAGS += -O3
else
    CFLAGS += -O0 -ggdb
endif

Answer 3

You can use target-specific variable values, they propagate to target's prerequisites:

all : foo bar
foo : CXXFLAGS += -DFOO
bar : CXXFLAGS += -DBAR

foo bar :
    @echo target=$@ CXXFLAGS=${CXXFLAGS}

.PHONY : all