Reverse bit order on VHDL

Question

I\'m having trouble doing something like

b(0 to 7) <= a(7 downto 0)

when I compile it with ghdl, I have an order error. The only way I have

Answer 1

There are several solutions for this problem. One possibility is the following:

gen: for i in 0 to 7 generate
  y(i) <= a(i) when rev='0' else a(7-i);
end generate;