Difference between “parameter” and “localparam”

Question

I\'m writing a project with Verilog and want to use parameter to define some parameter in my module. But when I read in some source code, localparam so

Answer 1

Minimal example

Here is an example of what Qiu mentioned.

In a RAM, the memory size is a function of the word and address sizes.

So if the parent module specifies word and address size, it should not be able to specify the memory size as well.

module myram #(
    parameter WORD_SIZE = 1,
    parameter ADDR_SIZE = 1
) (
    input wire [ADDR_SIZE-1:0] addr,
    inout wire [WORD_SIZE-1:0] data,
    // ...
);
    localparam MEM_SIZE = WORD_SIZE * (1 << ADDR_SIZE);
    // Use MEM_SIZE several times in block.
...

And on parent module, this is fine:

module myram_tb;
    myram #(
        .ADDR_SIZE(2),
        .WORD_SIZE(2)
    ) top (
        /* wires */
    )

but this should be an error:

module myram_tb;
    myram #(
        .ADDR_SIZE(2),
        .WORD_SIZE(2),
        .MEM_SIZE(2)
    ) top (
        /* wires */
    )

iverilog doesn't fail, and I believe that this is a bug: https://github.com/steveicarus/iverilog/issues/157

Incisive gives an error as expected.