How to Synthesize While Loop in Verilog?

Question

I have tried to design a Booth multiplier and it runs well in all compilers including:

Modelsim,Verilogger Extreame,Aldec Active Hdl & Xilinx\'s Isim......<

Answer 1

Here are some tips:

• Remove the latches:
  • c[5:1] is a latch because it is not initialized in the if(a==5'b10000) branch.
  • d is not defined in if(a==5'b10000) and could be a potential latch depending on the synthesizer optimization capabilities.
  • e is not defined in if(b==5'b10000) and could be a potential latch like d.
  • At the beginning of the always block, make sure all the combination logic have initial values.
• Try to avoid using disable for code to be synthesized. Use if-else statements instead.
  • Note: This is a guideline not a rule.
• There is lot of redundant and poorly organized code:
  • All branches with in the case statement are the same. Should be cleaned up in consolidated.
  • There is code inside the while loop that is better suited outside the loop (e.g. the if(count*==3'b101) block)
• If the while loop is having problems, try a for loop.