Display signal name/literal in test bench

Question

Is it possible to reference/display the name/literal of a signal in Verilog?

This would be a useful feature for creating a general signal checking function in a Verilog

Answer 1

In Verilog, the only way is by writing C code with the PLI/VPI.

In SystemVerilog, you can use a quoting macro

`define QUOTE(q) `"q`"
`define DISPLAY(me) $display("Signal %s is %h",`QUOTE(me), me)

`DISPLAY(my_signal);