Synchronous vs Asynchronous Resets in FPGA system

Question

I\'m new to creating a FPGA system to drive an I2C Bus (although I imagine that this problem applies to any FPGA system) using a variety of different modules, and which all use

Answer 1

@Stuart Vivian

(this should be posted as comment but I don't have enough reputation points to do so, sorry about that)

Consider using a counter instead of a shift register for delaying resets because if a LUT content is not cleared after loading the bitstream (some FPGA families have this behaviour), the reset signal may bounce, leading to unpredictable results.