I\'m having some issues with the makefile I made:
CC=gcc # Compiler variable
CFLAGS=-Wall -m32 # Options passed to the compiler
DEPS =
Here:
source1.o: source1.c
$(CC) -o source1 source1.c $(CFLAGS)
You have specified the output file as source1 when you meant source1.o. This should be:
source1.o: source1.c
$(CC) -c -o source1.o source1.c $(CFLAGS)
You can use automatic variables like $@ (for the target) and $< (for the first prerequisite) to avoid silly typos like that.