How to implement clock frequency multiplier using VHDL

Question

I am a beginner in VHDL coding. I am trying to implement frequency multiplier using VHDL. I have implemented frequency divider, but frequency multiplier is not that easy. Ple

Answer 1

A clock frequency can be divided using flip-flops. However, clock multiplication cannot be performed by purely digital circuits. As mentioned by Morten, a PLL unit (which is a hybrid circuit, thus not directly implemented with VHDL) is used for that. PLLs are built-in units in FPGAs, so all that you have to do is to instantiate them.

A detailed example on how to do it is in Appendix G of "Circuit Design and Simulation with VHDL", by V. Pedroni. Several complete examples usign PLLs for clock multiplication in data serializers are also included in that book.