Verilog Loop Condition

Question

I am completely new to verilog and I have to know quite a bit of it fairly soon for a course I am taking in university. So I am play around with my altera DE2 board and quartis2

Answer 1

The block will trigger every time there is a positive edge of the clock. Where you had a while loop does not mean anything in hardware, it would still need a clock to drive the flip flops.

While loops can be used in testbeches to drive stimulus

integer x;
initial begin
  x = 0;
  while (x<1000) begin
    data_in = 2**x ; //or stimulus read from file etc ...
    x=x+1;
  end
end

I find for loops or repeat to be of more use though:

integer x;
initial begin
  for (x=0; x<1000; x=x+1) begin
    data_in = 2**x ; //or stimulus read from file etc ...
  end
end

initial begin
  repeat(1000) begin
    data_in = 'z; //stimulus read from file etc (no loop variable)...
  end
end

NB: personally I would also add begin end to every thing to avoid adding extra lines later and wondering why they always or never get executed, especially while new to the language. It also has the added benefit of making the indenting look a little nicer.

always@ (posedge CLOCK_50 or negedge reset_n) begin
  if(!reset_n) begin
    count <= 'b0;
  end
  else if (enable) begin
    count <= count + 1;
  end
end