Verilog Loop Condition

Question

I am completely new to verilog and I have to know quite a bit of it fairly soon for a course I am taking in university. So I am play around with my altera DE2 board and quartis2

Answer 1

I don't think you want to use a while loop there. How about:

   always@ (posedge CLOCK_50 or negedge reset_n) begin
           if(!reset_n)
               count <= 0;
           else if (enable)
               count <= count + 1;
    end

I also added non-blocking assignments <=, which are more appropriate for synchronous logic.