How to NOT use while() loops in verilog (for synthesis)?

Question

I\'ve gotten in the habit of developing a lot testbenches and use for() and while() loops for testing purpose. Thats fine. The problem is that I\'ve taken this habit over to cod

Answer 1

If your synthesis tool does not support while or for loops, then don't use a loop. Just expand your code out.

wire [1:0] addr;
reg  [3:0] wren;

always @(posedge clk) begin
    wren[0] <= (addr == 2'd0);
    wren[1] <= (addr == 2'd1);
    wren[2] <= (addr == 2'd2);
    wren[3] <= (addr == 2'd3);
end

I am unfamiliar with XST, but some synthesis tools do support loops (Synopsys, for example).