Verilog Blocking Assignment

Question

I am somewhat new to Verilog. I know that in a Clock Process we should use non blocking assignments, and in a Non Clock processes, we use blocking assignments.

I have c

Answer 1

By only changing to code to blocking assignments it may synthesize to latches and/or create logical equivalency check mismatches depending on the tools handle.

This is how it looks through the scheduler:

• With blocking:

  1. The *_int signals are assigned
  2. The *_met signals are assigned
  3. Move on to the next time step.
     • *_int keeps the non-updated values of *_met

• With non-blocking:

  1. The *_int signals are assigned
  2. The *_met signals are assigned
  3. A change to *_met is detected causes a loop back the the Active region of the scheduler
  4. Re-assign the *_int signals
  5. Re-assign the *_int signals
  6. Move on to the next time step.
     • *_int has the same values as *_met
     • Waste CPU time to reprocessing. This is not important on a small project, but can add noticeable overhead used throughout a large project.

The correct, logical equivalent, and CPU friendly way would be to revers the assignment order (assign *_met before *_int):

always@(*)
begin
  iowrb_met = iowr_bar;
  iordb_met = iord_bar;

  iowrb_int = iowrb_met;
  iordb_int = iordb_met;
end

1. The *_int signals are assigned
2. The *_met signals are assigned
3. Move on to the next time step.
   • *_int has the same values as *_met

OR use *_bar as the assigning value (i.e. if a==b and b==c, then a==b and a==c):

always@(*)
begin
  iowrb_int = iowr_bar;
  iordb_int = iord_bar;

  iowrb_met = iowr_bar;
  iordb_met = iord_bar;
end

1. The *_int and *_met signals are assigned
2. Move on to the next time step.
   • *_int has the same values as *_met