Verilog Blocking Assignment

Question

I am somewhat new to Verilog. I know that in a Clock Process we should use non blocking assignments, and in a Non Clock processes, we use blocking assignments.

I have c

Answer 1

The main difference is:

• a blocking assignment is executed before the next assignment i.e. it blocks the execution of the next statement.
• non-blocking assignments execute in parallel i.e. they don't block the execution of the statement following them.

Suppose a = 2 and b = 3 then non-blocking assignments:

a <= 4;
b <= a; 

results in a = 4 and b = 2 - value of a before assignment

But

a = 4;
b = a;

Will result in a=4 and b=4 - value of a after the blocking assignment completes.

A variable getting synthesized to a register (latch or flip-flop) vs. combinatorial logic depends on the sensitivity list of the always block. It does not depend on use of blocking or non-blocking assignment.

For example:

always @(*) begin
  if (enable)
     q = d;
end

This will result in a D-latch since assignment to q is not specified for when enable==0 so it needs to remember is last assignment.

While

always @(*) begin
  if (enable)
    q = d;
  else
    q = f;
end

This will result in a mux (combinatorial logic) since assignment to q is specified for both cases of enable and so q need not remember anything.