Use a generic to determine (de)mux size in VHDL?

Question

I want to use a generic \'p\' to define how many outputs a demux will have. Input and all outputs are 1 bit. The outputs, control, and input can be something simple like:<

Answer 1

You need to feed log_p as generic and compute p as you go.

library ieee;
use ieee.std_logic_1164.all;
entity demux is
    generic (
        log_p: integer);
    port(
        control : in std_logic_vector(log_p downto 0);
        input :in std_logic;
        outputs : out std_logic_vector(2**log_p - 1 downto 0)
        );
end entity demux;