VHDL synthesis warning FF/Latch has a constant value of 0

Question

I\'m trying out some code that essentially involves using an FPGA and reading values from a temperature sensor.

The code is below:

library IEEE;
use          


        

Answer 1

I guess, this warning (FF/Latch) occurs when we forget to assign some value for some signals (or even maybe we think that it is not necessary to assign some value), especially when there are some conditions like if-else. It is expected that for all conditions we assign a value. So, it makes our code neatly and also long to repeat some assignment in every condition, but we can set an initial value for all those signals (which the FF/Latch warning refers to them) exactly after begin of a process and before if rising-edge. For example, in STATE_Transition procecc, between begin and if rising_edge, you should write write_temp <= (others=>'0').