VHDL synthesis warning FF/Latch has a constant value of 0

Question

I\'m trying out some code that essentially involves using an FPGA and reading values from a temperature sensor.

The code is below:

library IEEE;
use          


        

Answer 1

Nothing is wrong here. The warning says that write_temp_0 is always 0 - that is, the warning only applies to bit 0 of write_temp, not the other 7 bits.

This is to be expected, as you never set bit 0 of write_temp to be anything but 0. The synthesizer picks up on this, and optimizes it by simply trimming it to be a constant 0 instead of being connected to logic.

So try out the code and see if it works - if it doesn't, it's probably due to other reasons.

Also, when writing and verifying code like this, the simulator is a fantastic tool - it'll allow you to locate logic errors in your code very easily. So no reason not to get to know how to use it.