When do signals get assigned in VHDL?

Question

Considering this code:

architecture synth of my_entity is
    signal a : std_logic;
begin

    a <= c and d;
    b <= a and c;

end synth;

Answer 1

Is the second line going to respect that a changed in the other process or are all signals only at the end of architecture assigned?

It sounds like you are thinking of signal behaviour within a single process when you say this. In that context, the signals are not updated until the end of the process, so the b update will use the "old" value of a

However, signal assignments not inside a process statement are executed continuously, there is nothing to "trigger" an architecture to "run". Or alternatively, they are all individual separate implied processes (as you have commented), with a sensitivity list implied by everything on the "right-hand-side".

In your particular case, the b assignment will use the new value of a, and the assignment will happen one delta-cycle after the a assignment.

For a readable description of how simulation time works in VHDL, see Jan Decaluwe's page here:

http://www.sigasi.com/content/vhdls-crown-jewel

And also this thread might be instructive:

https://groups.google.com/group/comp.lang.vhdl/browse_thread/thread/e47295730b0c3de4/d5bd4532349aadf0?hl=en&ie=UTF-8&q=vhdl+concurrent+assignment#d5bd4532349aadf0