When do signals get assigned in VHDL?

Question

Considering this code:

architecture synth of my_entity is
    signal a : std_logic;
begin

    a <= c and d;
    b <= a and c;

end synth;

Answer 1

Careful with your terminology. When you say a changed in the other "process", that has a specific meaning in VHDL (process is a keyword in VHDL), and your code does not have any processes.

Synthesizers will treat your code as:

a <= c and d;
b <= (c and d) and c;

Simulators will typically assign a in a first pass, then assign b on a second pass one 'delta' later. A delta is an infinitesimal time delay that takes place at the same simulation time as the initial assignment.

Note this is a gross generalization of what really happens...if you want full details, read up on the documentation provided with your tool chain.