Why the %r0 of SPARC or MIPS, is always 0?

Question

I know that when you read %r0 in SPARC CPU (and MIPS), always return 0, but I like to know Why ?

What design decision is behind this and why ?

Answer 1

The main reason from instruction-set-design point of view is that the existance of a /dev/null-register allows for certain "condensing" of what otherwise would have to be two (or more) different instructions into a single one. Few examples:

• function call and return, using link registers, can be done with a single instruction:
  • As function call instruction: jmp ,,
    (SPARC jmp is an atomic mov ,; mov ,), and
  • As function return instruction: jmp ,,
• cmp or tst can be a simple sub ,,

Complete tables of these can be found from Oracle's documentation, SPARC synthetic instructions and sparcv9 synthetic instructions; most of these involve %g0 somewhere.