Way to initialize synthesizable 2D array with constant values in Verilog

Question

in VHDL, I can easily do this:

constant    cmdbytes       : bytearray(0 to Total) := (x\"05\", x\"00\", x...};

I want synthesizable constan

Answer 1

module test (

   input [7:0]   p1_sa,            // i
   input [7:0]   p1_sb,            // i
   output [7:0]   p3,            // o
   output [7:0]   p3b            // o
);

logic [7:0] array2d [7:0] = {99,124,119,123,242,107,111,197};

   assign p3    = array2d[p1_sa];
   assign p3b   = array2d[p1_sb];

endmodule

I tried the above system verilog code and it is working fine in modelsim and Vivado.