Way to initialize synthesizable 2D array with constant values in Verilog

Question

in VHDL, I can easily do this:

constant    cmdbytes       : bytearray(0 to Total) := (x\"05\", x\"00\", x...};

I want synthesizable constan

Answer 1

Verilog 2005 doesn't allow array initialization. Though your FPGA vendor should have a means to generate a ROM.