How to receive L1, L2 & L3 cache size using CPUID instruction in x86

Question

I encountered a problem during preparing an assembler x86 project which subject is to write a program getting L1 data, L1 code, L2 and L3 cache size.

I tried to fi

Answer 1

For Intel CPUs:

• for newer CPUs you should use "CPUID, eax=0x00000004" (with different values in ECX)

• for older CPUs (that don't support the first option) you should use "CPUID, eax=0x00000002". This involves having a table to look up what the values mean. There are cases where the same value means different things for different CPUs and you need addition information (e.g. CPU family/model/stepping).

For VIA CPUs; use the same methods as you would for Intel (with different tables for anything that involves "family/model/stepping").

For AMD CPUs:

• for newer CPUs you should use "CPUID, eax=0x8000001D" (with different values in ECX)

• for older CPUs (that don't support the first option) you should use "CPUID, eax=0x80000006" (for L2 and L3 only), plus "CPUID, eax=0x80000005" (for L1 only).

For all other cases (very old Intel/VIA/AMD CPUs, CPUs from other manufacturers):

• use CPU "vendor/family/model/stepping" (from "CPUID, eax=0x0000001") with a table (or maybe 1 table per vendor) so you can search for the right CPU in your table/s and get the information that way.

• if CPUID is not supported there are ways to try to narrow down the possibilities and determine what the CPU is with reasonable accuracy; but mostly you should just give up.

In addition; for all CPUs you should trawl through the errata sheets to see if CPUID provides wrong information; and implement work-arounds to correct that wrong information.

Note that (depending on which range of CPUs you support and awesome you want your code to be) it can take several months of work just to extract reliable information about caches.