Does each core has its own private set of registers?

Question

Looking from this intel core i7 nehalem microarchitecure

It seems that each co

Answer 1

Each core has its own set of registers, MMU, TLB, level 1 caches (data and instruction), level 2 cache (this depends on processor) etc. Cache Coherency is supported across cores via "QPI" and in the case of high end Core 7 and server-based processors like Xeon, Cache Coherency is supported across processors on a multi-processor mother board by exposing "QPI" on the external pins of those processors (for processors where multi-processor cache coherency is not supported, "QPI" is not "exposed").

Wiki article: Nehalem