VHDL driving signal from different processes

Question

I have a little problem with following VHDL code:

process (zbroji)
begin
    if rising_edge(zbroji) then
        oduzima <= \'0\';
        ucitanPrvi <         


        

Answer 1

When you're changing same signal value from multiple process, the simulator will be creating multiple signal drivers for this. The output of them will essentially will be unresolved. Think of it as the output of multiple gates connected together, what do you expect?

To overcome this, what you need to implement is, a resolution function, that drivers the output to signal.

http://www.csee.umbc.edu/portal/help/VHDL/misc.html#resf

If you have any doubts, let me know.