VHDL driving signal from different processes

Question

I have a little problem with following VHDL code:

process (zbroji)
begin
    if rising_edge(zbroji) then
        oduzima <= \'0\';
        ucitanPrvi <         


        

Answer 1

Unless zbroji and oduzmi are seperate clocks this is my recommended implementation

This registers the zbroji and oduzmi and checks if the value in the register is the opposite of the original signal. This should only occur when zbroji/oduzmi go from 0 to 1 and the register has not yet updated the change in signal.

process (clk)
begin
    if rising_edge(clk) then
        if zbroji = '1' and zbroji_old = '0' then
            oduzima <= '0';
            ucitanPrvi <= '1';
            broj1 <= ulaz_broj;
        elif oduzmi = '1' and oduzmi_old = '0' then
            oduzima <= '1';
            ucitanPrvi <= '1';
            broj1 <= ulaz_broj;
        end if;
        zbroji_old <= zbroji;
        oduzmi_old <= oduzmi;
    end if;
end process;

Also it appears that ucitanPrvi and broj1 are always the same thing. Either the signals are useless, this was orignally a typo or you are creating "update" pulses in which case you need the statement

    ucitanPrvi <= '0'
    broj1 <= (others=>'0') -- assumed reset?

following the if(rising_edge(clk) statement