VHDL driving signal from different processes

Question

I have a little problem with following VHDL code:

process (zbroji)
begin
    if rising_edge(zbroji) then
        oduzima <= \'0\';
        ucitanPrvi <         


        

Answer 1

Driving signals from multiple processes is a bad idea unless you really know what you're doing. You can re-write this code in a single process like this.

process (zbroji, oduzmi)
begin
    if rising_edge(zbroji) then
        oduzima <= '0';
        ucitanPrvi <= '1';
        broj1 <= ulaz_broj;
    end if;
    if rising_edge(oduzmi) then
        oduzima <= '1';
        ucitanPrvi <= '1';
        broj1 <= ulaz_broj;
    end if;
end process;

Note that if you do this, and you get a rising edge on both zbroji & oduzmi then oduzima will get the value 1 as it happens last in the process. Before you'd have been trying to set it to 0 and 1 at the same time. That would simulate to X, and probably wouldn't synthesize. If it did synthesize you'd be connecting power and ground together in a CMOS design.

---

An alternative method is to have each process drive it's own version of the signal, and then resolve them externally with what ever function you like (or another process). In this case I used or:

process (zbroji)
begin
    if rising_edge(zbroji) then
        ucitanPrvi_1 <= '1';
    end if;
end process;

process (oduzmi)
begin
    if rising_edge(oduzmi) then
        ucitanPrvi_2 <= '1';
    end if;

end process;

ucitanPrvi <= ucitanPrvi_1 or ucitanPrvi_2;