How are the modern Intel CPU L3 caches organized?

Question

Given that CPUs are now multi-core and have their own L1/L2 caches, I was curious as to how the L3 cache is organized given that its shared by multiple cores. I would imagin

Answer 1

Modern Intel L3 caches (since Nehalem) use a 64B line size, the same as L1/L2. They're shared, and inclusive.

See also http://www.realworldtech.com/nehalem/2/

Since SnB at least, each core has part of the L3, and they're on a ring bus. So in big Xeons, L3 size scales linearly with number of cores.

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See also Which cache mapping technique is used in intel core i7 processor? where I wrote a much larger and more complete answer.