VHDL: creating a very slow clock pulse based on a very fast clock

Question

(I\'d post this in EE but it seems there are far more VHDL questions here...)

Background: I\'m using the Xilinx Spartan-6LX9 FPGA with the

Answer 1

Note for this example to work this line,

signal clk_enable_counter : std_logic_vector(9 downto 0);

must be changed to

signal clk_enable_counter : unsigned(9 downto 0);

and you'll need to include this library,

library ieee; use ieee.numeric_std.all;