Handling parameterization in SystemVerilog packages

Question

SystemVerilog added packages to provide namespaces for common code pieces (functions, types, constants, etc). But since packages are not instantiated, they cannot be parame

Answer 1

I know that this is a very old post but I have been struggling with this issue for quite some time now. I believe I have found a suitable solution but I don't currently have the toolset to verify if this can synthesize successfully.

See section 5.6.7 in: http://www.sutherland-hdl.com/papers/2013-SNUG-SV_Synthesizable-SystemVerilog_paper.pdf

By using a static parameterized class with static functions, you can call different parameterizations of each data type on the fly and keep them unique for each instantiation.

Can anyone verify that this is a viable solution? Thanks!