Handling parameterization in SystemVerilog packages

Question

SystemVerilog added packages to provide namespaces for common code pieces (functions, types, constants, etc). But since packages are not instantiated, they cannot be parame

Answer 1

I wouldn't say it's a missing feature. What you're trying to do has been done with macros in Verilog for decades. Trouble is you've got to be rather unique in the way you name things to avoid clashes between packages. It's not nice, but it works.

Parameters are a bit different. They are for customising on an instance by instance basis (like VHDL generics). Either on modules for logic, or classes for test-benches. My only criticism of them is once you start using them they tend to propagate throughout your hierarchy, and the syntax isn't exactly compact. Very powerful though, and great for code re-use.