Handling parameterization in SystemVerilog packages

Question

SystemVerilog added packages to provide namespaces for common code pieces (functions, types, constants, etc). But since packages are not instantiated, they cannot be parame

Answer 1

This may or may not apply, depending on exactly what you have in mind to put in the package, but interfaces can be parameterized and are synthesizable if your tool supports it.

There is an example at http://www.doulos.com/knowhow/sysverilog/tutorial/interfaces/