Handling parameterization in SystemVerilog packages

Question

SystemVerilog added packages to provide namespaces for common code pieces (functions, types, constants, etc). But since packages are not instantiated, they cannot be parame

Answer 1

Yeah, I agree. That's a missing feature of packages.

Just spitballin' here, but you could abstract your parameters into a secod package and use the right one at compile-time to tweak your package. I know that's not what you really want, but it might get you close.

I think I would just end up with multiple packages representing each configuration if I faced this in my project.