What is the difference between == and === in Verilog?

Question

What is the difference between:

if (dataoutput[7:0] == 8\'bx) begin

and

if (dataoutput[7:0] === 8\'bx) begin 

Answer 1

== For comparing bits (0 or 1) === For comparing all 4 states (0, 1, x, z)

== can be synthesized into a hardware (x-nor gate), but === can't be synthesized as x is not a valid logic level in digital, it is infact having voltages in between 0 and 1. And z is not itself any logic, it shows disconnection of the circuit.