What is the difference between == and === in Verilog?

Question

What is the difference between:

if (dataoutput[7:0] == 8\'bx) begin

and

if (dataoutput[7:0] === 8\'bx) begin 

Answer 1

In Verilog:

• == tests logical equality (tests for 1 and 0, all other will result in x)
• === tests 4-state logical equality (tests for 1, 0, z and x)