Read textfile in VHDL testbench

Question

I have a file source.txt, it looks like this:

00660066006700670067006800680069006B006D006E
00660066006700670067006800680069006B006D006E
00660066         


        

Answer 1

Using VHDL-2008, and showing the std_logic_vector underway, the code can be:

library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;

entity tb is
end entity;

architecture syn of tb is
begin
  process is
    variable line_v : line;
    file read_file : text;
    file write_file : text;
    variable slv_v : std_logic_vector(44 * 4 - 1 downto 0);
  begin
    file_open(read_file, "source.txt", read_mode);
    file_open(write_file, "target.txt", write_mode);
    while not endfile(read_file) loop
      readline(read_file, line_v);
      hread(line_v, slv_v);
      report "slv_v: " & to_hstring(slv_v);
      hwrite(line_v, slv_v);
      writeline(write_file, line_v);
    end loop;
    file_close(read_file);
    file_close(write_file);
    wait;
  end process;
end architecture;