VHDL state machine differences (for synthesization)

Question

I am taking a class on embedded system design and one of my class mates, that has taken another course, claims that the lecturer of the other course would not let them imple

Answer 1

Ugh. I hate the dual process state machine thing personally. He is probably an old guy and this was the most reliable way to do it 20 years ago. The tools understand your way and I personally like that approach better.