VHDL state machine differences (for synthesization)

Question

I am taking a class on embedded system design and one of my class mates, that has taken another course, claims that the lecturer of the other course would not let them imple

Answer 1

the first method looks more fool proof since everything is clocked and there is less (no?) risk of introducing latches.

Yes, the first method where everything is clocked has no chance of introducing latches. It may introduce flipflops, but that's fine.

The 2nd method can introduce true asynchronous latches, which even in the best case are not very well handled by the back end FPGA tools I've used, and are not supported at all in some architectures, so would have to be built out of gates or lookup-tables.

In addition, if you get your sensitivity list wrong in the second process, your simulation can differ from your synthesis result! This is because synthesisers (for reasons I've given up trying to understand) treat the sensitivity list as if it were populated with all the signals you read (completely ignoring the VHDL language spec in the process) whereas the simulator will do exactly what you said.