AND all elements of an n-bit array in VHDL

Question

lets say I have an n-bit array. I want to AND all elements in the array. Similar to wiring each element to an n-bit AND gate.

How do I achieve this in VHDL?

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Answer 1

My favorite, non-VHDL-2008 solution is:

use ieee.std_logic_unsigned.all ;  -- assuming not VHDL-2008
. . . 
result <= '1' when not MyArray = 0 else '0' ; 

With VHDL-2008, I recommend that you use the "and" reduction built-in (see Pedroni's post) and use the IEEE standard package "ieee.numeric_std_unsigned.all" instead of the shareware package "std_logic_unsigned".