AND all elements of an n-bit array in VHDL

Question

lets say I have an n-bit array. I want to AND all elements in the array. Similar to wiring each element to an n-bit AND gate.

How do I achieve this in VHDL?

<

Answer 1

If you have VHDL-2008 available, then reduction and is build into the language as David Koontz and Pedroni have explained.

If you only have VHDL-2003 and prior available, then you can use a function like:

function and_reduct(slv : in std_logic_vector) return std_logic is
  variable res_v : std_logic := '1';  -- Null slv vector will also return '1'
begin
  for i in slv'range loop
    res_v := res_v and slv(i);
  end loop;
  return res_v;
end function;

You can then use the function both inside and outside functions with:

signal arg : std_logic_vector(7 downto 0);
signal res : std_logic;
...
res <= and_reduct(arg);